1. Field of the Invention
The present invention relates to a semiconductor device (insulated gate semiconductor device) having an insulated gate electrode region and a method of manufacturing it, and more particularly to an insulated gate semiconductor device suitable for power use and a method of manufacturing it.
2. Description of the Related Art
Insulated gate semiconductor devices such as a MOSFET and an IGBT (insulated gate bipolar transistor) are widely used as power semiconductor devices which are used in the power electronics field in recent years. In order to make power converters more efficient or more compact, the semiconductor device is demanded not to suffer from a large loss but to have high-speed switching. Measures therefor are considered to decrease a gate capacitance which is parasitically present in a MIS gate structure of the insulated gate semiconductor device.
Meanwhile, there are known problems that when the gate capacitance is decreased, the tolerance to noise is degraded and a malfunction occurs. The gate capacitance is comprised of a parasitic capacitance Cg1 (also called as feedback capacitance) between a gate electrode and a high voltage side main electrode (a drain electrode or a collector electrode) and a parasitic capacitance Cg2 between a gate electrode and a low voltage side main electrode (a source electrode or an emitter electrode). If the capacitance Cg2 is excessively small, the electric potential (namely, gate voltage) of the gate electrode against that of the low voltage side main electrode becomes susceptible to an influence of a noise.
Prior art which improves noise tolerance is disclosed in Patent Literature 1 indicated below. It describes that the capacitance Cg1 is decreased intensively at only a portion where the capacitance Cg1 is structurally generated by increasing the thickness of the gate insulating film. However, this structure requires a special process when it is produced and has a high difficulty level. The reduction of the capacitance Cg1 is limited because it merely depends on the thickness of the formed gate insulating film. [patent Literature 1] Japanese Patent Laid-Open Application No. Hei 8-274301